LVDS2_CLK_SEL=ARM_PLL, LVDS1_CLK_SEL=ARM_PLL
Miscellaneous Register 1
| LVDS1_CLK_SEL | This field selects the clk to be routed to anaclk1/1b.Not related to PMU. 0 (ARM_PLL): Arm PLL 1 (SYS_PLL): System PLL 2 (PFD4): ref_pfd4_clk == pll2_pfd0_clk 3 (PFD5): ref_pfd5_clk == pll2_pfd1_clk 4 (PFD6): ref_pfd6_clk == pll2_pfd2_clk 5 (PFD7): ref_pfd7_clk == pll2_pfd3_clk 6 (AUDIO_PLL): Audio PLL 7 (VIDEO_PLL): Video PLL 9 (ETHERNET_REF): ethernet ref clock (ENET_PLL) 12 (USB1_PLL): USB1 PLL clock 13 (USB2_PLL): USB2 PLL clock 14 (PFD0): ref_pfd0_clk == pll3_pfd0_clk 15 (PFD1): ref_pfd1_clk == pll3_pfd1_clk 16 (PFD2): ref_pfd2_clk == pll3_pfd2_clk 17 (PFD3): ref_pfd3_clk == pll3_pfd3_clk 18 (XTAL): xtal (24M) |
| LVDS2_CLK_SEL | This field selects the clk to be routed to anaclk2/2b.Not related to PMU. 0 (ARM_PLL): Arm PLL 1 (SYS_PLL): System PLL 2 (PFD4): ref_pfd4_clk == pll2_pfd0_clk 3 (PFD5): ref_pfd5_clk == pll2_pfd1_clk 4 (PFD6): ref_pfd6_clk == pll2_pfd2_clk 5 (PFD7): ref_pfd7_clk == pll2_pfd3_clk 6 (AUDIO_PLL): Audio PLL 7 (VIDEO_PLL): Video PLL 8 (MLB_PLL): MLB PLL 9 (ETHERNET_REF): ethernet ref clock (ENET_PLL) 10 (PCIE_REF): PCIe ref clock (125M) 11 (SATA_REF): SATA ref clock (100M) 12 (USB1_PLL): USB1 PLL clock 13 (USB2_PLL): USB2 PLL clock 14 (PFD0): ref_pfd0_clk == pll3_pfd0_clk 15 (PFD1): ref_pfd1_clk == pll3_pfd1_clk 16 (PFD2): ref_pfd2_clk == pll3_pfd2_clk 17 (PFD3): ref_pfd3_clk == pll3_pfd3_clk 18 (XTAL): xtal (24M) 19 (LVDS1): LVDS1 (loopback) 20 (LVDS2): LVDS2 (not useful) |
| LVDSCLK1_OBEN | This enables the LVDS output buffer for anaclk1/1b |
| LVDSCLK2_OBEN | This enables the LVDS output buffer for anaclk2/2b |
| LVDSCLK1_IBEN | This enables the LVDS input buffer for anaclk1/1b |
| LVDSCLK2_IBEN | This enables the LVDS input buffer for anaclk2/2b |
| PFD_480_AUTOGATE_EN | This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off |
| PFD_528_AUTOGATE_EN | This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off |
| IRQ_TEMPPANIC | This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature |
| IRQ_TEMPLOW | This status bit is set to one when the temperature sensor low interrupt asserts for low temperature |
| IRQ_TEMPHIGH | This status bit is set to one when the temperature sensor high interrupt asserts for high temperature |
| IRQ_ANA_BO | This status bit is set to one when when any of the analog regulator brownout interrupts assert |
| IRQ_DIG_BO | This status bit is set to one when when any of the digital regulator brownout interrupts assert |